As the term is used herein, “integrated circuit” includes devices such as those formed on monolithic semiconducting substrates, such as those formed of group IV materials like silicon or germanium, or group III-V compounds like gallium arsenide, or mixtures of such materials. The term includes all types of devices formed, such as memory and logic, and all designs of such devices, such as MOS and bipolar. The term also comprehends applications such as flat panel displays, solar cells, and charge coupled devices.
Integrated circuits are typically formed through a series of photolithographic processes, where photoresist is applied across the surface of the substrate on which the integrated circuits are fabricated. The photoresist is exposed with a pattern that remains in the photoresist after it is developed. Processing is then accomplished in some manner through the voids that are formed in the patterned photoresist. For example, the exposed portions of the integrated circuits being fabricated can be etched, receive deposited layers, or be doped, such as with ion implantation.
Because of the small geometries and tight tolerances of modern integrated circuits, there is a need to align one lithographic layer to another with a high degree of accuracy. One method of accomplishing this is an indirect alignment method, where for the first alignment layer, alignment reference marks on the substrate are aligned with reference marks disposed on the stage of the exposure tool. Subsequent layers are aligned by aligning the reference marks on the reticle to the reference marks on the stage of the exposure tool. The exposure is then made with the reticle being indirectly aligned.
An alternate method uses a direct alignment, where the alignment reference marks on the reticle for the second and subsequent layers are aligned directly to the reference marks that were formed on the substrate when the first layer was printed. The exposure is then made with the reticle being directly aligned. With either of these two methods, after the alignment is performed, the alignment results can be augmented with second order corrections that are determined from overlay measurements of previous substrates.
The approaches described above focus on aligning reference marks on the substrate, such as from the first layer, to reference marks on the reticle, for the second and subsequent layers, either directly or indirectly. This is typically limited to a very small number of reference marks when augmentation is not used. When augmentation is used, the number of reference marks may be extended to a number of marks that covers the exposure field corners at multiple sites across the substrate, and may additionally include a mark at the field center.
However, each of the cases described are generally limited to a fairly modest number of points that are aligned. For layers that do not have demanding overlay requirements, such a low number of alignment marks may be adequate. However, there tends to be inherent errors between the reticles used for the first layer and those used for the second and subsequent layers. This includes differences in where the alignment marks are placed with respect to each other, differences in where the alignment marks are placed with respect to the circuit pattern, and differences in the internal layout of the circuit pattern. When overlay demands become very stringent, these inherent errors can start to consume a significant portion of the overlay budget.
What is needed, therefore, is a system that overcomes problems such as those described above, at least in part.